1. Field of the Invention
The embodiments relate to asynchronous pipeline processing. More particularly, the embodiments relate to an asynchronous pipeline circuit with variable request signal delay, a method for asynchronous pipeline processing with variable request signal delay and a method for incorporating variable request signal delay into an asynchronous pipeline circuit design.
2. Description of the Related Art
In data processing, a pipeline typically refers to an integrated circuit having multiple stages of logic blocks (i.e., multiple stages of combinational logic) that are connected in series so that the output of one stage (i.e., data-out) is the input of the next stage (i.e., data-in). A synchronous pipeline refers to a pipeline in which registers are inserted between the various stages and synchronously clocked to ensure that any data being transferred between stages is stable. That is, between each of the stages in a synchronous pipeline, a register is clocked so that the data-in to the logic block of a receiving stage is the final data-out from the logic block of the transmitting stage. An asynchronous pipeline refers to a pipeline that uses a handshaking protocol, rather clocked registers, to pass data from one stage to the next stage. That is, a transmitting stage performs its logic function (i.e., propagates data through its logic block) and also asserts a request signal to indicate to a receiving stage (i.e., the next stage in the pipeline) that new data is available for capture. Then, upon receipt of the request signal, the receiving stage captures this new data and asserts an acknowledge signal back to the transmitting stage to acknowledging receipt.
Asynchronous pipelines avoid issues related to clocking (e.g., additional power requirements, management of clock skew, interfacing with environments clocked at different rates, etc.). However, for the handshaking protocol to work properly, the path traveled by the request signal (i.e., the request signal path) must be carefully timed so that the request signal arrives at the receiving stage only after the data processed by the logic block in the transmitting stage is stable (i.e., only after data propagation through the logic block in the transmitting stage is complete). Traditionally, the timing requirements of the request signal are met by inserting a buffer into the request signal path. Such a buffer ensures that a fixed request signal delay, which is greater than or equal to the maximum possible processing time that could be required for propagation of data through the logic block of the transmitting stage. Oftentimes, however, a logic block within a given stage of the asynchronous pipeline circuit will have completed data processing prior to the expiration of the fixed request signal delay for that stage. As a result, the stage must sit idle waiting for the request signal delay to expire. Therefore, it would be advantageous to provide an improved asynchronous pipeline circuit that minimizes the amount of time during which pipeline stages sit idle (e.g., waiting for a fixed request signal delay to expire) in order to decrease overall pipeline processing time.